The present invention relates to a frequency detection circuit for detecting whether the clock frequency is within standards in a unit such as CPU or a device such as EEPROM.
It is generally known that the CPU or the EEPROM operates erroneously or suffers runaway when the clock frequency applied externally varies to a great extent. Accordingly, in order to prevent the erroneous operation and protect data of the EEPROM, a frequency detection circuit has hitherto been used which detects whether the frequency is within standards.
FIG. 7 is a circuit diagram of a conventional frequency detection circuit and FIGS. 8A-8F are time charts of voltage waveforms at essential portions of the frequency detection circuit of FIG. 7. The frequency detection circuit has inverter gates 21 to 31, capacitors 32 and 33, N-channel transistors 34 and 35 and a NOR gate 36.
A signal CLK to be measured is a clock signal as shown in FIG. 8A and when it is at "H" level, the output of the inverter gate 21 assumes "L" level, so that a P-channel MOS transistor in the inverter gate 22 of C-MOS push-pull type is turned on and the capacitor 32 is charged to power supply voltage VDD (see FIG. 9) in accordance the time determined by a time constant of an on-resistance of the P-channel transistor and a capacitance of the capacitor 32. When the measured signal CLK subsequently falls to "L", the output of the inverter 21 changes to "H" and consequently, an N-channel MOS transistor in the inverter gate 22 is turned on and the electric charge stored in the capacitor 32 is discharged in accordance with the time determined by a time constant of an on-resistance of the N-channel transistor and the capacitance of the capacitor 32. Through this operation, output A3 of the inverter gate 22 takes a waveform as shown in FIG. 8B.
Output B3 of the inverter gate 23 as shown in FIG. 8C is determined depending on whether the output A3 of the gate 22 crosses a threshold value Vth3 supplied to the inverter gate 23, though not illustrated.
Similarly, since the capacitor 33 is charged in accordance with a time constant determined by an on-resistance of a P-channel MOS transistor in the inverter gate 25 and a capacitance of the capacitor 33 and is discharged in accordance with a time constant determined by an on-resistance of an N-channel MOS transistor in the inverter gate 25 and the capacitance of the capacitor 33, output C3 of the inverter gate 25 takes a waveform as shown in FIG. 8D. Then, the level of output of the inverter gate 26 is determined depending on whether the output C3 of the gate 25 crosses a threshold value Vth4 supplied to the inverter gate 26, though not illustrated.
When the frequency of the measured signal CLK is "S" which is smaller as compared to the time constants, more strictly, when 1/2 of the period corresponding to the frequency "S" is larger than the time constants, the output C3 of the inverter gate 25 alternately crosses the threshold value Vth4 of the inverter gate 26. As a result, output D3 of the inverter gate 27 takes a waveform in which "H" level and "L" level appear alternately as shown in FIG. 8E. Here, the inverter gates 28 to 31, the N-channel transistors 34 and 35 and the NOR gate 36 cooperate with each other to perform such an operation that when the measured signal CLK is "H", output OUT of the NOR gate 36 assumes "L" and at the time that the measured signal CLK changes to "L" and the output D3 of the inverter gate 27 keeps its state (here, "L" level), the output OUT of the NOR gate 36 keeps "L" level as shown in FIG. 8F. Thus, when the frequency of the measured signal CLK is "S", the output OUT of the NOR gate 36 is fixed to "L" level as shown in FIG. 8F.
Subsequently, when the frequency of the measured signal CLK changes at time to "F" which is larger as compared to the time constants, more strictly, when 1/2 of the period corresponding to the frequency "F" is smaller than the time constants, the output C3 of the inverter gate 25 does not cross the threshold value Vth4 of the inverter gate 26 and the output D3 of the inverter gate 27 keeps "H" level. Consequently, by the action of the inverter gates 28 to 31, the transistors 34 and 35 and the NOR gate 36 in combination, the output OUT of the NOR gate 36 becomes identical to inversion of the measured signal CLK.
Thus, in the frequency detection circuit of FIG. 7, the frequency of the measured signal CLK in excess of a specified frequency is determined depending on whether the output OUT of the NOR gate changes to "H" level.
The conventional frequency detection circuit, however, faces a problem that the detection frequency varies with variations in power supply voltage. More particularly, each of the C-MOS push-pull type inverter gates 22 and 25 is constructed of a P-channel MOS transistor and an N-channel MOS transistor as shown in FIG. 9. In the frequency detection circuit, each of the capacitors 32 and 33 is charged and discharged in accordance with time constants determined by on-resistances of these P-channel and N-channel transistors and a capacitance of each of the capacitors 32 and 33, and the results of charge/discharge (FIGS. 8B and 8D) are compared with the threshold values Vth3 and Vth4 of the inverter gates 23 and 26 of the succeeding stages to detect a specified boundary frequency. But, since the on-resistance of each of the P-channel and N-channel transistors greatly varies as the power supply voltage varies, the result of charge/discharge of each of the capacitors 32 and 33 changes greatly and so the detection frequency varies.
In addition, when the terminal voltage C3 of the capacitor 33 does not cross the threshold value Vth4 of the inverter gate 26, the output OUT of the NOR gate 36 changes to "H" level and hence, the on-resistance at the time that the N-channel transistor in the inverter gate 25 is turned on during discharge of the capacitor 33 is particularly important. But, conductance gm of the N-channel transistor which determines the on-resistance has large irregularities due to manufacture, raising a problem that irregularity in the on-resistance of the N-channel transistor degrades the accuracy of detection frequency.